MSL 54S112DM - MSL FPGA INC 專門從事 MSL MEISHILONG 可編程邏輯器件 FPGA 的設計與製造


Product Number	MSL 54S112DM
Category	觸發器
Package	16-CDIP
Packing Method	散裝
Description	J-K FLIP-FLOP
Parameters	功能:設置（預設）和複位\|類型:JK 型\|輸出類型:補充型\|元件數:2\|每個元件位數:1\|時鐘頻率:60 MHz\|不同 V、最大 CL 時最大傳播延遲:12ns @ 5V，50pF\|觸發器類型:負邊沿\|電流 - 輸出高、低:1mA，20mA\|電壓 - 供電:4.5V ~ 5.5V\|電流 - 靜態 (Iq):50 mA\|輸入電容:-\|工作溫度:-55°C ~ 125°C（TA）

Product Number

MSL 54S112DM

Category

觸發器

Package

16-CDIP

Packing Method

散裝

Description

J-K FLIP-FLOP

Parameters

Contact Us:

MSL FPGA INC (USA)
Registered Address: 1312 17th Street Unit #2199, Denver, CO 80202
Email: mslus@mslsemi.com

MSL FPGA PTE. LTD. (Singapore)
Registered Address: 709 Ang Mo Kio Avenue 8 #01-2591, Singapore 560709
Email: mslsingapore@mslsemi.com

Meishilong Technology Co., Ltd. (Hong Kong)
Registered Address: Rm A1-13, Blk A 3/F, Yee Lim Industrial Centre, 2-28 Kwai Lok Street, Kwai Chung NT, Hong Kong
Email: mslhk@mslsemi.com

Meishilong Technology (Shenzhen) Co., Ltd.
2603M, Dingcheng International Building, No.7 Zhonghang Road, Huahang Community, Huaqiangbei Street, Futian District, Shenzhen
Email: mslchina@mslsemi.com

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