MSL CDCR61APWR - MSL FPGA INC 專門從事 MSL MEISHILONG 可編程邏輯器件 FPGA 的設計與製造


Product Number	MSL CDCR61APWR
Category	應用特定時鐘抖定時
Package	16-TSSOP
Packing Method	卷帶（TR）
Description	IC DIRECT RAMBUS CLK GEN 16TSSOP
Parameters	PLL:是\|主要用途:記憶體，RDRAM\|輸入:晶體\|輸出:LVCMOS\|電路數:1\|比率 - 輸入:1：2\|差分 - 輸入:無/是\|頻率 - 最大值:400MHz\|電壓 - 供電:3V ~ 3.6V\|工作溫度:0°C ~ 85°C

Product Number

MSL CDCR61APWR

Category

應用特定時鐘抖定時

Package

16-TSSOP

Packing Method

卷帶（TR）

Description

IC DIRECT RAMBUS CLK GEN 16TSSOP

Parameters

Contact Us:

MSL FPGA INC (USA)
Registered Address: 1312 17th Street Unit #2199, Denver, CO 80202
Email: mslus@mslsemi.com

MSL FPGA PTE. LTD. (Singapore)
Registered Address: 91 Bencoolen Street #12-03, Sunshine Plaza, Singapore 189652
Email: mslsingapore@mslsemi.com

Meishilong Technology Co., Ltd. (Hong Kong)
Registered Address: Rm A1-13, Blk A 3/F, Yee Lim Industrial Centre, 2-28 Kwai Lok Street, Kwai Chung NT, Hong Kong
Email: mslhk@mslsemi.com

Meishilong Technology (Shenzhen) Co., Ltd.
2603M, Dingcheng International Building, No.7 Zhonghang Road, Huahang Community, Huaqiangbei Street, Futian District, Shenzhen
Email: mslchina@mslsemi.com

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