MSL MAX9450EHJ - MSL FPGA INC 專門從事 MSL MEISHILONG 可編程邏輯器件 FPGA 的設計與製造


Product Number	MSL MAX9450EHJ
Category	應用特定時鐘抖定時
Package	32-TQFP（5x5）
Packing Method	散裝
Description	PLL BASED CLOCK DRIVER, 9450 SER
Parameters	PLL:是\|主要用途:3G，以太網，SONET/SDH\|輸入:LVCMOS，LVDS，LVPECL\|輸出:LVPECL\|電路數:1\|比率 - 輸入:2：2\|差分 - 輸入:是/是\|頻率 - 最大值:160MHz\|電壓 - 供電:2.4V ~ 3.6V\|工作溫度:-40°C ~ 85°C

Product Number

MSL MAX9450EHJ

Category

應用特定時鐘抖定時

Package

32-TQFP（5x5）

Packing Method

散裝

Description

PLL BASED CLOCK DRIVER, 9450 SER

Parameters

Contact Us:

MSL FPGA INC (USA)
Registered Address: 1312 17th Street Unit #2199, Denver, CO 80202
Email: mslus@mslsemi.com

MSL FPGA PTE. LTD. (Singapore)
Registered Address: 91 Bencoolen Street #12-03, Sunshine Plaza, Singapore 189652
Email: mslsingapore@mslsemi.com

Meishilong Technology Co., Ltd. (Hong Kong)
Registered Address: Rm A1-13, Blk A 3/F, Yee Lim Industrial Centre, 2-28 Kwai Lok Street, Kwai Chung NT, Hong Kong
Email: mslhk@mslsemi.com

Meishilong Technology (Shenzhen) Co., Ltd.
2603M, Dingcheng International Building, No.7 Zhonghang Road, Huahang Community, Huaqiangbei Street, Futian District, Shenzhen
Email: mslchina@mslsemi.com

Message

Online Message