MSL AD1846JP - MSL FPGA INC 專門從事 MSL MEISHILONG 可編程邏輯器件 FPGA 的設計與製造


Product Number	MSL AD1846JP
Category	編解碼器
Package	68-PLCC（24.23x24.23）
Packing Method	散裝
Description	16-BIT STEREO CODEC
Parameters	類型:身歷聲音頻\|數據介面:並聯\|解析度（位）:16 b\|ADC/DAC 數:2 / 2\|三角積分:無\|信噪比，ADC/DAC (db)（典型值）:-\|動態範圍，ADC/DAC (db) 典型值:75 / 83\|電壓 - 供電，模擬:5V\|電壓 - 供電，數字:5V\|工作溫度:0°C ~ 70°C（TA）

Product Number

MSL AD1846JP

Category

編解碼器

Package

68-PLCC（24.23x24.23）

Packing Method

散裝

Description

16-BIT STEREO CODEC

Parameters

Contact Us:

MSL FPGA INC (USA)
Registered Address: 1312 17th Street Unit #2199, Denver, CO 80202
Email: mslus@mslsemi.com

MSL FPGA PTE. LTD. (Singapore)
Registered Address: 709 Ang Mo Kio Avenue 8 #01-2591, Singapore 560709
Email: mslsingapore@mslsemi.com

Meishilong Technology Co., Ltd. (Hong Kong)
Registered Address: Rm A1-13, Blk A 3/F, Yee Lim Industrial Centre, 2-28 Kwai Lok Street, Kwai Chung NT, Hong Kong
Email: mslhk@mslsemi.com

Meishilong Technology (Shenzhen) Co., Ltd.
2603M, Dingcheng International Building, No.7 Zhonghang Road, Huahang Community, Huaqiangbei Street, Futian District, Shenzhen
Email: mslchina@mslsemi.com

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